Method of fabricating vertical structure leds

ABSTRACT

A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to semiconductor devicefabrication. More particularly, the present invention relates to amethod of fabricating vertical devices using a metal support layer.

[0003] 2. Discussion of the Related Art

[0004] Light emitting diodes (“LEDs”) are well-known semiconductordevices that convert electrical current into light. The color(wavelength) of the light that is emitted by an LED depends on thesemiconductor material that is used to fabricate the LED. This isbecause the wavelength of the emitted light depends on the semiconductormaterial's band-gap, which represents the energy difference between thematerial's valence band and conduction band electrons.

[0005] Gallium-Nitride (GaN) has gained much attention from LEDresearchers. One reason for this is that GaN can be combined with indiumto produce InGaN/GaN semiconductor layers that emit green, blue, andwhite light. This wavelength control ability enables an LEDsemiconductor designer to tailor material characteristics to achievebeneficial device characteristics. For example, GaN enables an LEDsemiconductor designer to produce blue LEDs, which are beneficial inoptical recordings, and white LEDs, which can replace incandescentlamps.

[0006] Because of the foregoing and other advantageous, the market forGaN-based LEDs is rapidly growing. Accordingly, GaN-basedopto-electronic device technology has rapidly evolved since theircommercial introduction in 1994. Because the efficiency of GaN lightemitting diodes has surpassed that of incandescent lighting, and is nowcomparable with that of fluorescent lighting, the market for GaN basedLEDs is expected to continue its rapid growth.

[0007] Despite the rapid development of GaN device technology, GaNdevices are too expensive for many applications. One reason for this isthe high cost of manufacturing GaN-based devices, which in turn isrelated to the difficulties of growing GaN epitaxial layers and ofsubsequently dicing out completed GaN-based devices.

[0008] GaN-based devices are typically fabricated on sapphiresubstrates. This is because sapphire wafers are commercially availablein dimensions that are suitable for mass-producing GaN-based devices,because sapphire supports relatively high-quality GaN epitaxial layergrowths, and because of the extensive temperature handling capability ofsapphire.

[0009] Typically, GaN-based devices are fabricated on 2″ diametersapphire wafers that are either 330 or 430 microns thick. Such adiameter enables the fabrication of thousands of individual devices,while the thickness is sufficient to support device fabrication withoutexcessive wafer warping. Furthermore, sapphire is chemically andthermally stable, has a high melting temperature that enables hightemperature fabrication processes, has a high bonding energy (122.4Kcal/mole), and a high dielectric constant. Chemically, sapphires arecrystalline aluminum oxide, Al₂O₃.

[0010] Fabricating semiconductor devices on sapphire is typicallyperformed by growing an n-GaN epitaxial layer on a sapphire substrateusing metal oxide chemical vapor deposition (MOCVD) or molecular beamepitaxy (MBE). Then, a plurality of individual devices, such as GaNLEDs, is fabricated on the epitaxial layer using normal semiconductorprocessing techniques. After the individual devices are fabricated theymust be diced out (separated) of the sapphire substrate. However, sincesapphires are extremely hard, are chemically resistant, and do not havenatural cleave angles, sapphire substrates are difficult to dice.Indeed, dicing typically requires that the sapphire substrate be thinnedto about 100 microns by mechanical grinding, lapping, and/or polishing.It should be noted that such mechanical steps are time consuming andexpensive, and that such steps reduce device yields. Even after thinningsapphires remain difficult to dice. Thus, after thinning and polishing,the sapphire substrate is usually attached to a supporting tape. Then, adiamond saw or stylus forms scribe lines between the individual devices.Such scribing typically requires at least half an hour to process onesubstrate, adding even more to the manufacturing costs. Additionally,since the scribe lines have to be relatively wide to enable subsequentdicing, the device yields are reduced, adding even more to manufacturingcosts. After scribing, the sapphire substrates can be rolled using arubber roller or struck with a knife-edge to produce stress cracks thatcan be used to dice out the individual semiconductor devices. Suchmechanical handling reduces yields even more.

[0011] Of note, because sapphire is an insulator the LED devicetopologies that are available when using sapphire substrates (or otherinsulating substrates) are, in practice, limited to lateral and verticaltopologies. In the lateral topology the metallic electrical contactsthat are used to inject electrical current into the LED are both locatedon upper surfaces (or on the same side of the substrate). In thevertical topology one metallic contact is on an upper surface, thesapphire (insulating) substrate is removed, and the other contact islocated on a lower surface.

[0012]FIGS. 1A and 1B illustrate a typical lateral GaN-based LED 20 thatis fabricated on a sapphire substrate 22. Referring now specifically toFIG. 1A, an n-GaN buffer layer 24 is formed on the substrate 22. Arelatively thick n-GaN layer 26 is formed on the buffer layer 24. Anactive layer 28 having multiple quantum wells ofaluminum-indium-gallium-nitride (AlInGaN) or of InGaN/GaN is then formedon the n-type GaN layer 26. A p-GaN layer 30 is then formed on theactive layer 26. A transparent conductive layer 32 is then formed on thep-GaN layer 30. The transparent conductive layer 32 may be made of anysuitable material, such as Ru/Au, Ni/Au or indium-tin-oxide (ITO). Ap-type electrode 34 is then formed on one side of the transparentconductive layer 32. Suitable p-type electrode materials include Ni/Au,Pd/Au, Pd/Ni and Pt. A pad 36 is then formed on the p-type electrode 34.Beneficially, the pad 36 is Au. The transparent conductive layer 32, thep-GaN layer 30, the active layer 28 and part of the n-GaN layer 26 areetched to form a step. Because of the difficulty of wet etching GaN, adry etch is usually used. This etching requires additional lithographyand stripping processes. Furthermore, plasma damage to the GaN stepsurface is often sustained during the dry-etch process. The LED 20 iscompleted by forming an n-electrode pad 38 (usually Au) and a pad 40 onthe step.

[0013]FIG. 1B illustrates a top down view of the LED 20. As can be seen,lateral GaN-based LEDs have a significant draw back in that having bothmetal contacts (36 and 40) on the same side of the LED significantlyreduces the surface area available for light emission. As shown in FIG.1B the metal contacts 36 and 40 are physically close together.Furthermore, as previously mentioned the pads 36 are often Au. Whenexternal wire bonds are attached to the pads 36 and 40, the Au oftenspreads. Au spreading can bring the electrical contacts even closertogether. Such closely spaced electrodes 34 are highly susceptible toESD damage.

[0014]FIGS. 2A and 2B illustrate a vertical GaN-based LED 50 that wasformed on a sapphire substrate that was subsequently removed. Referringnow specifically to FIG. 2A, the LED 50 includes a GaN buffer layer 54having an n-metal contact 56 on a bottom side, and a relatively thickn-GaN layer 58 on the other. The n-metal contact 56 is beneficiallyformed from a high reflectively layer that is overlaid by a highconductivity metal, including, for example, Au. An active layer 60having multiple quantum wells is formed on the n-type GaN layer 58, anda p-GaN layer 62 is formed on the active layer 60. A transparentconductive layer 64 is then formed on the p-GaN layer 62, and a p-typeelectrode 66 is formed on the transparent conductive layer 64. A pad 68is formed on the p-type electrode 66. The materials for the variouslayers are similar to those used in the lateral LED 20. The verticalGaN-based LED 50 as the advantage that etching a step is not required.However, to locate the n-metal contact 56 below the GaN buffer layer 54the sapphire substrate (not shown) has to be removed. Such removal canbe difficult, particularly if device yields are of concern. However, asdiscussed subsequently, sapphire substrate removal using laser lift offis known.

[0015] Referring now to FIG. 2B, vertical GaN-based LEDs have theadvantage that only one metal contact (68) blocks light. Thus, toprovide the same amount of light emission area, lateral GaN-based LEDsmust have a larger surface area, which lowers device yields.Furthermore, the reflecting layer of the n-type contact 56 of verticalGaN-based LEDs reflect light that is otherwise absorbed in lateralGaN-based LEDs. Thus, to emit the same amount of light as a verticalGaN-based LED, a lateral GaN-based LED must have a significantly largersurface area. Because of these issues, a 2″ diameter sapphire wafer canproduce about 35,000 vertical GaN-based LEDs, but only about 12,000lateral GaN-based LEDs. Furthermore, the lateral topology is morevulnerable to static electricity, primarily because the two electrodes(36 and 40) are so close together. Additionally, as the lateral topologyis fabricated on an insulating substrate, and as the vertical topologycan be attached to a heat sink, the lateral topology has relatively poorthermal dissipation. Thus, in many respects the vertical topology isoperationally superior to the lateral topology.

[0016] However, most GaN-based LEDs fabricated with a lateral topology.This is primarily because of the difficulties of removing the insulatingsubstrate and of handling the GaN wafer structure without a supportingsubstrate. Despite these problems, removal of an insulation (growth)substrate and subsequent wafer bonding of the resulting GaN-based waferon a Si substrate using Pd/In metal layers has been demonstrated forvery small area wafers, approx. 1 cm by 1 cm. But, substrate removal andsubsequent wafer bonding of large area wafers remains very difficult dueto inhomogeneous bonding between the GaN wafer and the 2^(nd)(substitutional) substrate. This is mainly due to wafer bowing duringand after laser lift off.

[0017] Thus, it is apparent that a new method of fabricating verticaltopology devices would be beneficial. In particular, a method thatprovides for mechanical stability of semiconductor wafer layers, thatenables vertical topology electrical contact formation, and thatimproves heat dissipation would be highly useful, particularly withdevices subject to high electrical currents, such as laser diodes orhigh-power LEDs. Beneficially, such a method would enable formingmultiple semiconductor layers on an insulating substrate, the adding ofa top support metal layer that provides for top electrical contacts andfor structural stability, and the removal of the insulating substrate.Of particular benefit would be a new method of forming partiallyfabricated semiconductor devices on a sapphire (or other insulating)substrate, the adding of a top support metal layer over the partiallyfabricated semiconductor layers, the removal of the sapphire (or otherinsulating) substrate, the formation of bottom electrical contacts, andthe dicing of the top support metal layer to yield a plurality ofdevices. Specifically advantageous would be fabrication process thatproduces vertical topology GaN-based LEDs.

SUMMARY OF THE INVENTION

[0018] The following summary of the invention is provided to facilitatean understanding of some of the innovative features unique to thepresent invention, and is not intended to be a fall description. A fullappreciation of the various aspects of the invention can be gained bytaking the entire specification, claims, drawings, and abstract as awhole.

[0019] The principles of the present invention provide for a method offabricating semiconductor devices on insulating substrates by firstforming semiconductor layers on the insulating substrate, followed byforming a metal layer over the semiconductor layers, followed by removalof the insulating substrate to isolate a structurally supported wafercomprised of the formed semiconductor layers and the metal layer. Themetal layer supports the semiconductor layers to prevent warping and/orother damage and provides for electrical contacts. Beneficially, themetal layer includes a metal, such as Cu, Cr, Ni, Au, Ag, Mo, Pt, Pd, W,or Al, or a metal containing material such as titanium nitride. Formingof the metal layer can be performed in numerous ways, for example, byelectroplating, by electro-less plating, by CVD, or by sputtering.Subsequently, bottom electrical contacts can be added to thesemiconductor layers and then individual semiconductor devices can bediced from the resulting structure.

[0020] The principles of the present invention further provide for amethod of fabricating vertical topology GaN-based devices on aninsulating substrate by the use of a metal support film and by thesubsequent removal of the insulating substrate. According to thatmethod, semiconductor layers for the GaN-based devices are formed on aninsulating (sapphire) substrate using normal semiconductor fabricationtechniques. Then, trenches that define the boundaries of the individualdevices are formed through the semiconductor layers. Those trenches mayalso be formed into the insulating substrate. Trench forming isbeneficially performed using inductive coupled plasma reactive ionetching (ICPRIE). The trenches are then filled with an easily removedlayer (such as a photo-resist). A metal support structure is then formedon the semiconductor layers. Beneficially, the metal support structureincludes a metal, such as Cu, Cr, Ni, Au, Ag, Mo, Pt, Pd, W, or Al, or ametal-containing material such as titanium nitride. Forming of the metalsupport structure can be performed in numerous ways, for example, byelectroplating, by electro-less plating, by CVD, or by sputtering. Theinsulating substrate is then removed, beneficially using a laser-liftoff process. Electrical contacts, a passivation layer, and metallic padsare then added to the individual devices, and the individual devices arethen diced out.

[0021] The principles of the present invention specifically provide fora method of fabricating vertical topology GaN-based LEDs on sapphiresubstrates. According to that method, semiconductor layers for thevertical topology GaN-based LEDs are formed on a sapphire substrateusing normal semiconductor fabrication techniques. Then, trenches thatdefine the boundaries of the individual vertical topology GaN-based LEDsare formed through the semiconductor layers. Those trenches may also beformed into the sapphire substrate. Trench forming is beneficiallyperformed using inductive coupled plasma reactive ion etching (ICPRIE).Beneficially, the trenches are fabricated using ICPRIE. The trenches arethen beneficially filled with an easily removed layer (such as aphoto-resist). A metal support structure is then formed on thesemiconductor layers. Beneficially, the metal support structure includesa metal, such as Cu, Cr, Ni, Au, Ag, Mo, Pt, Pd, W, or Al, or ametal-containing material such as titanium nitride. Forming of the metallayer can be performed in numerous ways, for example, by electroplating,by electro-less plating, by CVD, or by sputtering. The sapphiresubstrate is then removed, beneficially using a laser-lift off process.Electrical contacts, a passivation layer, and metallic pads are thenadded to the individual LEDs, and the individual LEDs are then dicedout.

[0022] The novel features of the present invention will become apparentto those of skill in the art upon examination of the following detaileddescription of the invention or can be learned by practice of thepresent invention. It should be understood, however, that the detaileddescription of the invention and the specific examples presented, whileindicating certain embodiments of the present invention, are providedfor illustration purposes only because various changes and modificationswithin the spirit and scope of the invention will become apparent tothose of skill in the art from the detailed description of the inventionand claims that follow.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying figures, in which like reference numerals referto identical or functionally-similar elements throughout the separateviews and which are incorporated in and form part of the specification,further illustrate the present invention and, together with the detaileddescription of the invention, serve to explain the principles of thepresent invention.

[0024] In the drawings:

[0025]FIG. 1A illustrates a sectional view of a typical lateral topologyGaN-based LED;

[0026]FIG. 1B shows a top down view of the GaN-based LED illustrated inFIG. 1A;

[0027]FIG. 2A illustrates a sectional view of a typical verticaltopology GaN-based LED;

[0028]FIG. 2B shows a top down view of the GaN-based LED illustrated inFIG. 2A; and

[0029] FIGS. 3-15 illustrate steps of forming a light emitting diodethat are in accord with the principles of the present invention.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

[0030] The principles of the present invention provide for methods offabricating semiconductor devices, such as GaN-based vertical topologyLEDs, on insulating substrates, such as sapphire substrates, using metalsupport films. While those principles are illustrated in a detaileddescription of a method of fabricating vertical topology GaN-based LEDson a sapphire substrate, those principles are broader than thatillustrated method. Therefore, the principles of the present inventionare to be limited only by the appended claims as understood under UnitedStates Patent Laws.

[0031] FIGS. 3-15 illustrate a method of manufacturing vertical topologyGaN-based light emitting diodes (LEDs) on sapphire substrates. Sapphiresubstrates are readily available in suitable sizes, are thermally,chemically, and mechanically stable, are relatively inexpensive, andsupport the growth of good quality GaN epitaxial layers. It should beunderstood that those figures are not to scale.

[0032] Referring now to FIG. 3, initially a GaN-based LED layerstructure is formed on a 330-430 micron-thick, 2″ diameter (0001)sapphire substrate 122. The GaN-based LED layer structure includes ann-GaN buffer layer 124, an InGaN/GaN active layer 126 (beneficiallyhaving the proper composition to emit blue light) on the buffer layer124, and a p-GaN contact layer 128 on the active layer 126.

[0033] Still referring to FIG. 3, the buffer layer 124 beneficiallyincludes both a 2 μm undoped GaN layer formed directly on the substrate,and a 1 μm thick, n-type, silicon doped, GaN layer. The p-GaN contactlayer 128 is beneficially about 0.05 μm thick and is doped with Mg.Overall, the GaN-based LED layer structure is beneficially less thanabout 5 microns thick. Various standard epitaxial growth techniques,such as vapor phase epitaxy, MOCVD, and MBE, together with suitabledopants and other materials, can be used to produce the GaN-based LEDlayer structure.

[0034] Referring now to FIG. 4, trenches 130 are formed through thevertical topology GaN-based LED layer structure. Those trenches 130 mayextend into the sapphire substrate 122. The trenches 130 define theindividual LED semiconductor structures that will be produced. Eachindividual LED semiconductor structure is beneficially a square about200 microns wide. The trenches 130 are beneficially narrower than about10 microns (preferably close to 1 micron) and extend deeper than about 5microns into the sapphire substrate 122. The trenches 130 assist asubsequent chip separation process.

[0035] Because of the hardness of sapphire and GaN, the trenches 130 arebeneficially formed in the structure of FIG. 3 using reactive ionetching, preferably inductively coupled plasma reactive ion etching (ICPRIE). Forming trenches using ICP RIE has two main steps: forming scribelines and etching. Scribe lines are formed on the structure of FIG. 3using a photo-resist pattern in which areas of the sapphire substrate122 where the trenches 130 are to be formed are exposed. The exposedareas are the scribe lines, while all other areas are covered byphoto-resist. The photo-resist pattern is beneficially fabricated from arelatively hard photo-resist material that withstands intense plasma.For example, the photo-resist could be AZ 9260, while the developer usedto develop the photo-resist to form the scribe lines could be AZ MIF500.

[0036] In the illustrated example, the photo-resist is beneficially spincoated to a thickness of about 10 microns. However, in general, thephoto-resist thickness should be about the same as the thickness of thevertical topology GaN-based LED layer structure plus the etch depth intothe sapphire substrate 122. This helps ensure that the photo-resist maskremains intact during etching. Because it is difficult to form a thickphoto-resist coating in one step, the photo-resist can be applied in twocoats, each about 5 microns thick. The first photo-resist coat is spincoated on and then soft baked, for example, at 90° F. for about 15minutes. Then, the second photo-resist coat is applied in a similarmanner, but is soft baked, for example, at 110° F. for about 8 minutes.The photo-resist coating is then patterned to form the scribe lines.This is beneficially performed using lithographic techniques anddevelopment. Development takes a relatively long time because of thethickness of the photo-resist coating. After development, thephoto-resist pattern is hard baked, for example, at about 80° F. forabout 30 minutes. Then, the hard baked photo-resist is beneficiallydipped in a MCB (Metal Chlorobenzene) treatment for about 3.5 minutes.Such dipping further hardens the photo-resist.

[0037] After the scribe lines are defined, the structure of FIG. 3 isetched. Referring now to FIG. 5, the ICP RIE etch process is performedby placing the structure of FIG. 3 on a bottom electrode 132 in a RIEchamber 134 having an insulating window 136 (beneficially a 1 cm-thickquartz window). The bottom electrode 132 is connected to a bias voltagesupply 138 that biases the structure of FIG. 3 to enable etching. Thebias voltage supply 138 beneficially supplies 13.56 MHz RF power and aDC-bias voltage. The distance from the insulating window 136 to thebottom electrode 132 is beneficially about 6.5 cm. A gas mixture of Cl₂and BCl₃, and possibly Ar, is injected into the RIE chamber 134 througha reactive gas port 140. Furthermore, electrons are injected into thechamber via a port 142. A 2.5-turn or so spiral Cu coil 144 is locatedabove the insulating window 136. Radio frequency (RF) power at 13.56 MHzis applied to the coil 144 from an RF source 146. It should be notedthat magnetic fields are produced at right angles to the insulatingwindow 136 by the RF power.

[0038] Still referring to FIG. 5, electrons present in theelectromagnetic field produced by the coil 144 collide with neutralparticles of the injected gases, resulting in the formation of ions andneutrals, which produce plasma. Ions in the plasma are acceleratedtoward the structure of FIG. 3 by the bias voltage applied by the biasvoltage supply 138 to the bottom electrode 132. The accelerated ionspass through the scribe lines, forming the etch channels 130 (see FIG.4).

[0039] Referring now to FIG. 6, after the trenches 130 are formed, thinp-contacts 150 are formed on the individual LED semiconductor structuresof the GaN-based LED layer structure. Those contacts 150 arebeneficially comprised of Pt/Au, Pd/Au, Ru/Au, Ni/Au, Cr/Au, or ofindium tin oxide (ITO)/Au and are less then 10 nm. Such contacts can beformed using a vacuum evaporator (electron beam, thermal, sputter),followed by thermal annealing at an intermediate temperature(approximately 300-700° C.).

[0040] As shown in FIG. 7, after the contacts 150 are formed, thetrenches 130 are filled with an easily removed material (beneficially aphoto-resist) to form posts 154.

[0041] Referring now to FIG. 8, after the posts 154 are formed, a metalsupport layer 156 approximately 50 μm is formed over the posts 154 andover the p-contacts 150. The posts 154 prevent the metal that forms themetal support layer 156 from entering into the trenches. The metalsupport layer 156 is beneficially comprised of a metal having goodelectrical and thermal conductivity and that is easily formed, such asby electroplating, by electro-less plating, by CVD, or by sputtering.Before electroplating or electro-less plating, it is beneficial to coatthe surface with a suitable metal, such as by sputtering. For example,the metal support layer 156 can be Cu, Cr, Ni, Au, Ag, Mo, Pt, Pd, W, orAl. Alternatively, the metal support layer 156 can be comprised of ametal-containing material such as titanium nitride.

[0042] Turning now to FIG. 9, the sapphire substrate 122 is then removedfrom the remainder of the structure using light 158 from an eximer layer(having a wavelength less than 350 nanometers), while the sapphiresubstrate is biased away from the remainder of the structure (such as byuse of vacuum chucks). The laser beam 158 passes through the sapphiresubstrate 122, causing localized heating at the junction of the sapphiresubstrate 122 and the n-GaN buffer layer 124. That heat decomposes theGaN at the interface of the sapphire substrate, which, together with thebias, causes the sapphire substrate 122 to separate, reference FIG. 10.It is beneficial to hold the other side of the structure with a vacuumchuck during laser lift off. This enable easy application of aseparation bias.

[0043] Laser lift off processes are described in U.S. Pat. No. 6,071,795to Cheung et al., entitled, “Separation of Thin Films From TransparentSubstrates By Selective Optical Processing,” issued on Jun. 6, 2000, andin Kelly et al. “Optical process for liftoff of group 111-nitridefilms”, Physica Status Solid (a) vol. 159, 1997, pp. R3-R4.Beneficially, the metal support layer 156 fully supports the individualLED semiconductor structures during and after separation of the sapphiresubstrate.

[0044] Still referring to FIG. 10, the posts 154 are then removed,leaving the trenches 130 behind.

[0045] Turning now to FIG. 11, the structure of FIG. 10 is inverted.Then, the side opposite the metal support layer 156 is cleaned with HClto remove Ga droplets (laser beam 158 heating separates GaN into Ga+N).After cleaning, ICP RIE polishing (using Cl₂ an/or Cl₂+BCl₃) isperformed to smooth the exposed surface (which is rough due to theseparation of the sapphire substrate). Polishing produces an atomicallyflat surface of pure n-GaN on the n-GaN buffer layer 124.

[0046] Turning now to FIG. 12, n-type ohmic contacts 160 are formed onthe n-GaN buffer layer 124 using normal semiconductor-processingtechniques. Beneficially, the n-type ohmic contacts 160 are comprised ofTi/Al-related materials.

[0047] Turning now to FIG. 13, to protect the semiconductor layers fromsubsequent processing, a passivation layer 162 is formed on the n-typeohmic contacts 160 and in the trenches 130. Electrical insulationcomprised Of SiO₂ or Si₃N₄ are suitable passivation layer materials.Additionally, as shown, the passivation layer 162 is patterned to exposetop surface portions of the n-type ohmic contacts 160.

[0048] Turning now to FIG. 14, after the passivation layer 162 isformed, metal pads 164 are formed on the n-type ohmic contacts 160. Asshown in FIG. 14, the metal pads 164 extend over portions of thepassivation layer 162. The metal pads 164 are beneficially comprised ofCr and Au.

[0049] After the metal pads 164 are formed, individual devices can bediced out. Referring now to FIG. 15, dicing is beneficially accomplishedusing photolithographic techniques to etch through the metal supportlayer 156 to the bottom of the passivation layer 162 (at the bottom ofthe trenches 130) and by removal of the passivation layer 162.Alternatively, sawing can be used. In practice, it is probably better toperform sawing at less than about 0° C. The result is a plurality ofvertical topology GaN LEDs 199 on conductive substrates.

[0050] The foregoing has described forming trenches 130 before laserlift off of the sapphire substrate 122. However, this is not required.The sapphire substrate 122 could be removed first, and then trenches 130can be formed.

[0051] The embodiments and examples set forth herein are presented tobest explain the present invention and its practical application and tothereby enable those skilled in the art to make and utilize theinvention. Those skilled in the art, however, will recognize that theforegoing description and examples have been presented for the purposeof illustration and example only. Other variations and modifications ofthe present invention will be apparent to those of skill in the art, andit is the intent of the appended claims that such variations andmodifications be covered. The description as set forth is not intendedto be exhaustive or to limit the scope of the invention. Manymodifications and variations are possible in light of the above teachingwithout departing from the spirit and scope of the following claims. Itis contemplated that the use of the present invention can involvecomponents having different characteristics. It is intended that thescope of the present invention be defined by the claims appended hereto,giving full cognizance to equivalents in all respects.

What is claimed is:
 1. A light-emitting device, comprising: a metallayer; a GaN contact layer adjacent the metal layer; a GaN buffer layer;a light-emitting layer disposed between the GaN contact layer and theGaN buffer layer; and an ohmic contact on the GaN buffer layer.
 2. Thelight-emitting device according to claim 1, further including a metallicpad over the ohmic contact.
 3. The light-emitting device according toclaim 1, further including a passivation layer over surfaces of the GaNcontact layer, of the light emitting layer, and of the GaN buffer layer.4. The light-emitting device according to claim 3, wherein thepassivation layer extends over part of the ohmic contact.
 5. Thelight-emitting device according to claim 3, wherein the passivationlayer includes a material selected from a group consisting of SiO₂ andSi₃N₄.
 6. The light-emitting device according to claim 1, wherein thelight emitting layer includes Ga.
 7. The light-emitting device accordingto claim 1, wherein the GaN contact layer is doped.
 8. Thelight-emitting device according to claim 1, wherein the metal layerincludes a metal selected from a group consisting of Cu, Cr, Ni, Au, Ag,Mo, Pt, Pd, W, and Al.
 9. The light-emitting device according to claim1, wherein the metal layer includes titanium nitride.
 10. A method ofproducing semiconductor devices, comprising: growing a plurality ofsemiconductor layers on an insulating substrate; forming first ohmiccontacts on the plurality of semiconductor layers; forming a metalsupport layer over the first ohmic contacts; removing the insulatingsubstrate; and forming second ohmic contacts on the plurality ofsemiconductor layers.
 11. A method of producing semiconductor devicesaccording to claim 10, further including the step of forming trenchesthrough the plurality of semiconductor layers, wherein the trenchesdefine a plurality of individual semiconductor devices.
 12. A method ofproducing semiconductor devices according to claim 11, wherein thetrenches extend into the insulating substrate.
 13. A method of producingsemiconductor devices according to claim 11, further including the stepof filling the trenches to form posts.
 14. A method of producingsemiconductor devices according to claim 13, wherein the metal supportlayer extends over the posts.
 15. The method of claim 10, furtherincluding passivating the plurality of semiconductor layers after theinsulating substrate is removed.
 16. The method of claim 15, whereinpassivation is performed after the second ohmic contacts are formed. 17.The method of claim 10, further including forming metal pads on thesecond ohmic contacts.
 18. The method of claim 10, further includingseparating out individual semiconductor devices.
 19. The method of claim18, wherein separating out individual semiconductor devices includesetching through the metal support layer.
 20. The method of claim 18,wherein separating out individual semiconductor devices includes sawingthrough the metal support layer.
 21. The method of claim 20, whereinsawing through the metal support layer is performed at a temperatureless than 0° C.
 22. The method of claim 10, wherein forming trenches isperformed using inductively coupled plasma reactive ion etching (ICPRIE).
 23. The method of claim 10, wherein removing the insulativesubstrate is performed using a laser lift off procedure.
 24. The methodof claim 23, wherein the laser lift off procedure includes radiatinglaser light through the insulative substrate.
 25. A method offabricating light emitting diodes, comprising: forming a GaN bufferlayer on a sapphire substrate; forming an active layer on the GaN bufferlayer; forming a GaN contact layer on the active layer; identifying thelocation of a plurality of individual light emitting diodes; forming afirst ohmic contact on each individual light emitting diode; forming ametal support structure over the first ohmic contacts; removing thesapphire substrate; and forming a second ohmic contact on eachindividual light emitting diode.
 26. A method of producing semiconductordevices according to claim 25, further including the step of formingtrenches through the plurality of semiconductor layers and betweenindividual semiconductor devices.
 27. A method of producingsemiconductor devices according to claim 26, wherein the trenches extendinto the sapphire substrate.
 28. A method of producing semiconductordevices according to claim 27, further including the step of filling thetrenches to form posts.
 29. A method of producing semiconductor devicesaccording to claim 28, wherein the metal support structure extends overthe posts.
 30. The method of claim 26, further including forming apassivation layer over exposed portions of the GaN buffer layer, of theactive layer, and of the GaN contact layer, wherein the passivationlayer is formed after the sapphire substrate is removed, and wherein thepassivation layer extends into the trenches.
 31. The method of claim 25,further including forming metal pads on the second ohmic contacts. 32.The method of claim 25, further including separating out individuallight emitting diodes.
 33. The method of claim 32, wherein separatingout individual light emitting diodes includes etching through the metalsupport structure.
 34. The method of claim 32, wherein separating outindividual light emitting diodes includes sawing through the metalsupport structure.
 35. The method of claim 34, wherein sawing throughthe metal support structure is performed at a temperature less than 0°C.
 36. The method of claim 26, wherein forming trenches is performedusing inductively coupled plasma reactive ion etching (ICP RIE).
 37. Themethod of claim 25, wherein removing the sapphire substrate is performedusing a laser lift off procedure.
 38. The method of claim 37, whereinthe laser lift off procedure includes radiating laser light through thesapphire substrate.
 39. The method of claim 25, wherein forming a metalsupport structure includes electroplating.
 40. The method of claim 25,wherein forming a metal support structure includes electro-less plating.41. The method of claim 25, wherein forming a metal support structureincludes CVD.
 42. The method of claim 25, wherein forming a metalsupport structure includes sputtering.